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VGA Demo

Verilog Instantiation Template: VGATimer #(800,64,120,56, 600,23,6,37, 1) timer (clk, hsync, vsync, active, x, y);

Sources:

• VGATimer.v
• VGATimer_single.v

Exemples:

• FPGA Chess Demo by Dragos Popescu

Test:

        module VGATestTop(clk, hsync, vsync, r1, r0, g1, g0, b1, b0);
            input clk;

            output hsync;
            output vsync;
            output r1, r0, g1, g0, b1, b0;
            wire r1, r0, g1, g0, b1, b0;

            wire active;
            wire [11:0] x;
            wire [11:0] y;

            VGATimer #(800,64,120,56, 600,23,6,37, 1) timer (clk, hsync, vsync, active, x, y);

            assign r1 = active&&(~(x[0]^y[0]));
            assign r0 = active&&(~(x[1]^y[1]));
            assign g1 = active&&(~(x[2]^y[2]));
            assign g0 = active&&(~(x[3]^y[3]));
            assign b1 = active&&(~(x[4]^y[4]));
            assign b0 = active&&(~(x[5]^y[5]));

        endmodule

Pictures:

• Bord
• VGA Demo 1
• VGA Demo 2