Tempap
     Mux_vs_3state
          Verilog
               Mux_tbuf16
                    mux_tbuf16.v
               Mux_gate16
                    mux_gate16.v
               Mux_tbuf
                    mux_tbuf.v
               Mux_gate
                    mux_gate.v
     FF_example
          Verilog
               ff_example.v
     OMUX_example
          Verilog
               omux_example.v
     GR_5K
          Verilog
               Active_low_GR
                    active_low_gr.v
               No_GR
                    no_gr.v
               Use_GR
                    use_gr.v
     GSR
          Verilog
               No_GSR
                    no_gsr.v
               Active_low_GSR
                    active_low_gsr.v
               Use_GSR
                    use_gsr.v
     Barrel_SR
          Verilog
               Barrel
                    S95.log
                    barrel.v
                    transcript
                    barrel.ER
               Barrel_org
                    barrel_org.v
                    S95.log
                    barrel_org.ER
     Bidir_LogiBLOX
          Verilog
               bidir_io_from_lb.mod
               logiblox.log
               bidir_logiblox.v
               bidir_logiblox.log
               bidir_io_from_lb.v
               bidir_io_from_lb.ngo
               logiblox.ini
               bidir_io_from_lb.vei
     D_register
          Verilog
               d_register.v
     Clock_mux
          Verilog
               clock_mux.v
     LogiBLOX_DP_RAM
          Verilog
               lb_dp_ram.ngo
               logiblox.log
               Back
                    lb_memfile.mem
               lb_dp_ram.mod
               logiblox_dp_ram.v
               lb_dp_ram.vei
               logiblox_dp_ram.log
               lb_memfile.mem
               lb_dp_ram.v
               logiblox.ini
     Gate_reduce
          Verilog
               Xilinx_dw
                    gate_reduce.v
                    xilinx_dw.v
               Synopsys_dw
                    gate_reduce.v
                    xilinx_dw.v
     Gate_clock
          Verilog
               readme.txt
               Gate_clock
                    gate_clock.ER
                    S95.log
                    gate_clock.v
               Gate_clock2
                    gate_clock.ER
                    S95.log
                    gate_clock.v
     Res_sharing
          Verilog
               Res_dw_no_share
                    res_sharing.v
               Res_sharing
                    res_sharing.v
               Res_dw_share
                    res_sharing.v
               Res_no_share
                    res_sharing.v
     5k_preset
          Verilog
               S95.log
               preset_5k.v
               preset_5k.ER
     Unbonded_IO
          Verilog
               S95.log
               unbonded_io.v
               unbonded_io.ER
     Bnd_scan_5k
          Verilog
               bnd_scan.v
               count4.v
     LogiBLOX_SR
          Verilog
               shifter_16.ngo
               logiblox.log
               shifter_16.v
               shifter_16.mod
               logiblox_sr.log
               logiblox_sr.v
               shifter_16.vei
               logiblox.ini
     Cap8.zip
     Case_vs_if
          Verilog
               Case_ex
                    case_ex.v
               If_ex
                    if_ex.v
     State_Machine
          Verilog
               Enum
                    enum.v
               One_Hot
                    one_hot.v
               Binary
                    binary.v
     Bidir_instantiate
          Verilog
               bidir_instantiate.v
     Bidir_infer
          Verilog
               bidir_infer.v
     RAM_primitive
          Verilog
               ram_primitive.v
               transcript
     D_latch
          Verilog
               d_latch.ER
               S95.log
               d_latch.v
     ROM_RTL
          Verilog
               S95.log
               rom_rtl.v
               rom_rtl.ER
     Clock_enable
          Verilog
               clock_enable.v
     Set_and_Reset
          Verilog
               set_and_reset.v
     Nested_if
          Verilog
               Nested_if
                    nested_if.v
               If_case
                    if_case.v
     Constants
          Verilog
               Parameter2
                    parameter2.v
               Parameter1
                    parameter1.v
     Bnd_scan_4k
          Verilog
               bnd_scan.v
               count4.v
disk1
     _isdel.exe
     setup.pkg
     _setup.1
     setup.ins
     disk1.id
     setup.ini
     _setup.lib
     setup.exe
     _inst32i.ex_
     _setup.dll
     setup.iss
disk2
     _setup.2
     disk2.id
veriwell-2.8.5.tar.gz